The present invention relates to the fabrication of integrated circuits and, more particularly, to a process technique for recessing tungsten with a substantially uniform recess depth for transistors having different channel (gate) lengths.
It is common in integrated circuit fabrication to require the formation of MOSFET transistor devices having different channel lengths. As is known to those skilled in the art, transistors of different lengths will have metal gate stacks of corresponding different lengths as well. After provision of the work function metal (WFM) for each metal gate stack, a deposit may be made of an overlying metal, such as tungsten, to form the gate electrode. A process step for recessing (i.e., partially removing) the deposited tungsten for each gate stack is then performed. However, it has proven to be difficult to achieve a uniform recess depth across the transistors of different lengths. The reasons for this include: a) etch loading effect; and b) differences in the tungsten materials for the transistors of different channel length (for example, differences in percent of barrier metal, differences in nucleation layer and differences in size of the tungsten grain boundary).
One solution which addresses the issue of achieving uniform recess depth is to implement a patterning mask to protect the devices having relatively longer channel (gate) lengths during the recess process. This solution, however, incurs an additional patterning cost and additional ash steps. There may also result in an adverse impact on the gate stack from performance of these processes.
There is accordingly a need in the art for a process technique that achieves a substantially uniform recess depth when recessing overlying metal, such as tungsten, in metal gate stacks for transistor devices have different channel (gate) lengths.